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lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 1 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a description key features the lx13088a is a highly integrated dual output voltage regulator ideal for low power applications that require minimal board space. the two current mode buck converters include integrated high side control switches, synchronous rectifiers, and internal compensation. the outputs of each converter are both rated for up to 1a, and the output voltages are adjustable using external resistive dividers. the lx13088a step down converters operate at 1.3mhz fixed switching frequency under normal load, reducing external output filter component values and size. under light load conditions, the converters operate in a pulse-skipping mode for improved efficiency. the lx13088a incorporates out of phase switching, where converter 2 switches 180 out of phase from converter 1 in order to minimize the input ripple effects. the controller also features an e/s pin that provides an enable input function, or allows the converter to be synchronized to an external clock. with the e/s input held low, the lx13088a draws less than 10ua. both converters have controlled soft start, in addition to power up sequencing. in the start-up sequ ence, the output of converter 1 is designed to precede the output of converter 2. power on reset function is provided by means of an open-d rain output at the por pin. the power on reset function monitors the voltages at the vmon, fb1 and fb2 pins, and pulls low if any of these voltages drop below the stated por threshold. the por is internally deglitched and provides a delayed recovery and reset time. the lx13088a provides peak over current protection, short circuit protection and thermal shutdown. discharge-before- turn-on discharges the outputs completely before soft starting to always bring them up in the proper sequence at start up or after a por event. ? outputs can be set from 1v to 3.6v @ 1a, vin dependent ? 3.0v to 5.5v operating input voltage range ? no rectifier diode required ? 1.3mhz switching ? 180 phase shifted switching ? optional external clocking (2x clock required) ? light load pulse skipping ? enable/sleep state ? internal soft start ? open-drain power on reset monitors input and outputs ? discharge before-turn-on ? peak over-current protection ? short circuit protection ? over temperature shutdown applications ? hard disk drives ? set- top boxes important: for the most current data, consult microsemi ?s website: http://www.microsemi.com product highlight package order info thermal data t a ( c) ld plastic 3x3 mm dfn 10-pin j a = 33 c/w rohs compliant / pb-free thermal resistance - junction to ambient 0 to +70 LX13088ACLD junction temperature calculation: t j = t a + (p d x ja numbers are guidelines for the thermal performance of the device/pc-board system. all of th e above assume no ambient airflow. note: available in tape & reel. append the letters ?tr? to the part number. (i.e. LX13088ACLD-tr)
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 2 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a absolute maximum ratings package pin out pvin, avin to agnd, pgnd ...................................................................... -0.3 to +7.0 v sw1 and sw2 to agnd, pgnd .................................................. p gnd -2v to xvin+2v all other pins to agnd .................................................................... -0.3 v to xvin + 0.3v operating junction te mperature range .......................................................... 0 0 c to 150 0 c storage temperat ure rang e..........................................................................?65 0 c to 150 0 c package peak temp. for solder reflow (40 seconds maximum exposure) .. 260c (+0 -5) 0 c notes: exceeding these ratings could cause damage to the de vice. all voltages are with respect to ground. currents are positive into, negative out of specifi ed terminal. pgnd must be wired to agnd externally. ld p ackage (top view) marking rohs / pb-free 100% matte tin finish functional pin description name pin # description fb2 1 feedback from vo2. connect voltage divider to the load side of vo2 output inductor-capacitor filter. avin 2 analog input. input to power the internal circ uitry of the device, connect to pvin through a 10 ? resistor and bypass through a 1 f ceramic capacitor between this pin and pgnd, as close to the lx13088a as possible. pvin 3 control mosfet switch power inputs. connect a 10f ceramic capacitor between this pin and pgnd, as close to the lx13088a as possible. sw2 4 converter 2 synchronous buck switching output. connect to vo2 inductor. pgnd 5 power ground connection. synchronous rectifier mosf et source. provide a star connection between this pin, vo1, vo2 filter capacitor retu rns, vin input capacitor return, and agnd. keep the star connection as close to the lx13088a ic as possible. sw1 6 converter 1 synchronous buck switching output. connect to vo1 inductor. e/s 7 enable/synchronization. pulling this pin high stat ically enables the lx13088a and pulling the pin low statically will shut down the lx13088a. applying a pulse to this pin will synchronize sw1 and sw2 switching frequency to ? the external clock frequency. por 8 power on reset output pin. monitors fb1, fb2 out put voltage levels and vin. por is pulled low if an output voltage droop is detected on fb1 or fb2 or vin, and is hi-z during normal operation. vmon 9 voltage monitor ? supervisor for one external voltage (c ould be input voltage). the por output is triggered if this output falls below the vmon threshold. fb1 10 feedback from vo1. connect voltage divider to the load side of vo1 output inductor-capacitor filter. agnd pad analog ground. connect the exposed pad on the botto m of the package to the gnd plane for a thermal heat sink. 088a date/lot code msc
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 3 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a electrical characteristics unless otherwise specified, the following specifications apply over the operating ambient temperature of 0 0 c < temp <70 0 c, and the following test conditions: 3.0 v vin 5 .5v, v pgnd = v agnd ; e/s = high (static) parameter symbol test conditions / comment min typ max units input circuitry operating input voltage v vin 3.0 5.5 v under voltage lockout v vin - uvlo v vin rising 2.4 2.7 2.85 v uvlo hysteresis 200 300 400 mv input supply current i vin t a = 25c; not switching; 1.2v = v fb1 = v fb2 0.01 0.6 1 m a e/s = low 0.1 10 a vmon input por threshold vmon v vmon- por v vmon falling (hysteresis = 20mv) 0.97 1.00 1.03 v vmon input current i vmon v vmon = 1.25v -100 0 100 na vo1 output feedback voltage v fb1 0.975 1.000 1.025 v peak current limit threshold i sw1-ct v vin = 3.0v 1.0 1.4 a v vin = 5.0v 1.2 1.6 pwm switching frequency f sw1 e/s = static logic high 1.3 mhz upper fet on resistance rds sw1-u t j = 25c , vin=3.3v 315 m ? t j = 25c, vin=5v 282 lower fet on resistance rds sw1-l t j = 25c, vin=3.3v 255 t j = 25c, vin=5v 226 soft start time t ss_fb1 0.5 1 2 ms por threshold fb1 v fb1-por fb1 falling (hysteresis = 2% v fb1 ) 87 89.5 92 %v fb1 discharge complete threshold v fb1-dct fb1 level where discharge cycle is terminated 50 75 100 mv vo2 output feedback voltage v fb2 0.975 1.000 1.025 v peak current limit i sw2-ct 1.2 1.6 a
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 4 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a electrical characteristics unless otherwise specified, the following specifications apply over the operating ambient temperature of 0 0 c < temp <70 0 c, and the following test conditions: 3.0 v vin 5 .5v, v pgnd = v agnd ; e/s = high (static) parameter symbol test conditions / comment min typ max units pwm switching frequency f sw2 e/s = static logic high 1.3 mhz upper fet on resistance rds sw2-u t j = 25c , vin=3.3v 290 m ? t j = 25c, vin=5v 255 lower fet on resistance rds sw2-l t j = 25c, vin=3.3v 170 t j = 25c, vin=5v 151 soft start time t ss_fb2 0.5 1 2 ms por threshold fb2 v fb2-por fb2 falling (hysteresis = 2% v fb2 ) 87 90 92 %v fb2 discharge complete threshold v fb2-dct fb2 level where discharge cycle is terminated 50 75 100 mv e/s e/s threshold v e/s - h 1.5 v v e/s - l 0.6 v e/s leakage current i e/s 0 < v e/s < v vin -100 100 na frequency lock in range f e/s - min switching frequency is ? e/s frequency when externally clocked. 1.5 mhz f e/s -max 3.0 shutdown delay t e/s-shdn shutdown initiated if logic low is of longer duration than delay. 2 4 10 s por por assert delay time t por_delay fault flag set to por pull low 25 s por release delay time t por_hold fault flag reset to por hi-z state 10 20 30 ms por low voltage v por_low por sinking 4ma 200 400 mv por high leakage i por_hi por high level 0.003 1 a power up sequencing vo2 start threshold v fb1-st fb1 rising voltage for fb2 to initiate soft start 87 90 93 %v fb1 brown out discharge sw1, sw2 discharge resistance r stop- sw1,2 discharge resistance for sw1 and vo2 15 30 45 ?
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 5 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a electrical characteristics unless otherwise specified, the following specifications apply over the operating ambient temperature of 0 0 c < temp <70 0 c, and the following test conditions: 3.0 v vin 5 .5v, v pgnd = v agnd ; e/s = high (static) parameter symbol test conditions / comment min typ max units sw1, sw2 discharge resistance matching r stop-sw1 / r stop- sw2 0.90 1 1.1 system characteristics unless otherwise specified, the following specifications apply over the operating ambient temperature of 0 0 c < temp <70 0 c, and the following test conditions:, 3.0 v vin 5.5v, e/s = high. configured per application circuit. sy stem characteristics are closed loop tests that are verified as part of characterization but are not tested in production. parameter symbol test conditions / comment min typ max units vo1 output line regulation vo1 i sw1(avg) = 300ma; 3.0v < v vin < 5.50v 0.1 % load regulation vo1 5ma < i sw1(avg) < 1000ma 0.5 % efficiency (l 1 dcr = 44m ? ) vin=5v figure 2 schematic vo1 i sw1(avg) = 1000ma; vo1= 2.5v 87 % i sw1(avg) = 200ma ; vo1= 2.5v 94 i sw1(avg) = 10ma; vo1= 2.5v 82 vo2 output line regulation vo2 i sw2(avg) = 300ma; 3.0v < v vin < 5.50v 0.1 % load regulation vo2 5ma < i sw2(avg) 1000ma 0.5 % efficiency (l 2 dcr = 44m ? ) vin=5v figure 2 schematic vo2 i sw2(avg) = 1000ma; vo2= 1.2v 80 % i sw2(avg) = 200ma; vo2= 1.2v 90 % i sw2(avg) = 10ma; vo2= 1.2v 75 thermal shutdown thermal shutdown threshold 160 c thermal shutdown hysteresis 20 c
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 6 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a startup sequencing softstart vin=5v, vout1=1.2v, vout2= 2.5v, both outputs loaded at 1a soft start showing converter 1, vout1=1.2v at 1a dynamic load efficiency vout1=1.2v, output 1 load transition from 0.5a to 1a efficiency for 2.5v and 1.2v output voltages, vin=5v
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 7 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a startup after output discharge synchronization outputs must discharge to <10% before repeat startup synchronization & out of phase, 3mhz clk in at e/s input current limit & short circuit output ripple vout1 shorted to ground continuously after normal regulation both outputs loaded at 1a, peak to peak output ripple is ~10mv
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 8 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a functional block diagram figure 1. functional block diagram
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 9 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a typical application figure 2. typical application circuit
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 10 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a theory of operation dc-dc s witching s tep d own c onverters the lx13088a dual dc-d c converters are current mode buck converters with integrated high side switch, synchronous rectifier and internal compensation. they are designed to be stable with a 3.3h inductor value and 10f to 22f output capacitor. both output voltages are resistor divider programmable. the switching frequency of the converter is fixed and the switches turn on at alternating 180 phase intervals. the converters operate in 3 possible modes: continuous mode (cm), discontinuous mode (dm), and pulse skipping mode (psm). cm is the default mode under normal loading. dm occurs under light loads, where switching still occurs at the programmed frequency. in dm, a zero crossing detector shuts off the synchronous rectifier to prevent reverse rectifier current; this results in a portion of the switch period where neither switch is on. under very light loads, psm mode occurs, where switching cycles are skipped if the current demand is low in order to provide better efficiency . both outputs are capable of providing a minimum of 1a output current capability when vin is within 4.5 to 5.5v. however as vin drops below this range, output vo1 current capability drops to 800ma. softstart the dc-dc converters cont ain a soft start function that brings the output voltages up via a slowly increasing ramp with any resistive load from open circuit to 1a. the output voltage waveform shall not vary by more than 50mv from a straight line drawn from the initial voltage to the final steady state voltage. during soft start, the peak inductor current shall not exceed 750ma until the output volta ge reaches 25% of its final value. current limit shall be active but not trip during soft start into a rated resistive load. overshoot voltage during soft start is limited to 1%. e nable and p ower u p s equencing when power is applied at vin and if the e/s input is asserted (high) or is toggling, the dc -dc converters will enter run mode after a short settling period. if the e/s pin is a static low, the ic will enter a sleep state where it draws very little input current, less than 10ua. when in run mode, if there is no fault condition, the vo1 output of converter will be the first output to begin soft start. when the reference voltage for fb1 reaches approximately 90% of the final value, the vo2 output of converter will begin soft start. por under-voltage comparators are provided to monitor the output voltages and the voltage at vmon which could be the input supply voltage. if any of these voltages falls below its por threshold, the por open drain output will turn on which pulls the por pin low. note that the fault to por assert delay time is approximately 20s. if the por fault condition is cleared, there is a delay of 20ms before the por output transistor is turned off; when off the por pin is high z and may be pulled up high via a resistor. the por function has built in deglitching. once the por is detected, the power supply outputs will be discharged prior to a restart condition, where soft st art and power up sequencing will occur. o utput d ischarge after the occurrence of a por situation, and the por fault condition is immediately cleared , startup and soft start is delayed until the outputs are discharge to <10%. during the discharge phase, the soft star t internal reference voltages (refx) are shorted to ground to quickly discharge it. the output capacitors are discharged via an internal 30 ? pull down switch on each of the sw1 and sw2 pins. when the fbx voltage and the refx voltage are fully discharged and if there is not an ot condition, the outputs are then allowed to begin the normal soft start power up sequence. duri ng the discharge phase, the control high side and synchronous rectifier mosfets are in the high-z off state. o ver current and short circuit p rotection the dc-dc converters have over current and short circuit protection. during any mode of operation, any value of load resistance (including 0 ohms) can be applied to the dc-dc outputs instantaneously and held in place indefinitely without the switch current exceeding the pe ak current limit and without the ic suffering any permanent damage or loss of performance. the output voltage is allowed to drop under over current or short circuit conditions. both converters will stop switching if either one experiences an over current condition for various cycles. recovery to output voltage regulation occurs within 10ms of the instant the loading is reduced to maximum allowable rated load; the output voltage sha ll not exceed the dynamic load excursion limits (+/-5% excursion) upon recovery.
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 11 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a operation e/s d ecoder l ogic the e/s pin serves a dual purpose. it will enable the ic if it detects either a valid clock signal or a static high logic level. a static low logic level for longer than 4s is determined to be a shutdown signal. the decode logic is shown below. the one- shot function will produce a logic high output (clock detect) as long as the e/s pin is toggling. clock detect is used to keep enable high and to select the e/s clock as the system clock. if e/s is a static high (non-toggling) input, the retriggerable one-shot will go low after 4s; this will set clk det low and select the internal oscillator as the system clock. s ynchronization the converters can be synchroni zed to an external system clock present at the e/s input pin. during synchronization, the converter?s switching frequency will be ? the frequency of the external clock, and the two converters will still be 180 degrees out of phase. the lock in frequency for synchronization is specified to be between 1.5mhz to 3mhz, minimum sync pulse width is 100ns. o ver temperature p rotection if an over temperature fau lt occurs, the dc-dc converter will stop switching and the sw# outputs will become high impedance. note that the temperature fault occurs at a die temperature of approximately 160 ? c. when the ic cools down, it will attempt to resume switching . if a por is activated as a result of the ot situation, restart will be subject to the soft start/sequencing routine and will not occur until the ot condition has been corrected. the device junction temperature is a function of the device?s total power dissipation, the junction to ambient thermal resistance, and the ambient temperature: ( ) + = the total power dissipated by the lx13088a device, p total, will be comprised of the power dissipated by the rms current flowing through the internal high-side fet during the duty cycle d time, by the rms cu rrent flowing through the synchronous rectifier during 1-d time, by the switching or transitioning of the fet, and of the power dissipated by the device supply current. i nductor s election a 3.3h 20% inductor is suggested as the internal compensation has been optimized around this inductor value. a 3.3h is a good compromise, since for an output voltage ranging from vout = 1v to vout = 4v, loaded at 1a, the lir or the ratio of inductor ripple current to output load will range from about 20% to 30%, assuming vin = 5v and the converter switching at 1.3mhz. o utput c apacitor to ensure stability and good load transient response, use at least a 10f output capacitor at vo1 output, and a 20f or greater at vo2 output. output ceramics capacitors with low esr are suitable. s etting the o utput v oltage the lx13088a converter?s maximum duty cycle is approximately 90%. for a 5v input, 90% duty cycle will be achieved for an output voltage of about 4v loaded at 1a. to set the output voltage, connect a resistive divider from the output to the fbx pin to signal ground. note that the feedback voltage is 1.0v. for the desired output voltage vout, the upper resistor from vout to fb (r upper ) is calculated by the following equation: ? ? ? ? ? ? ? = 1 vfb vout lower r upper r r lower, or the resistor from fbx pin to ground, is selected to be 20k ? . vfb = 1v, and vout is chosen by the designer for the given application. m aximum d uty c ycle device maximum duty cycle is typically 89%. the output capability of the device will be limited to the maximum duty cycle. for example, for vin= 3.3v, vout=2.5v at 1a load, the device will be near its maximum duty cycle. thus, lowering the input voltage below 3.3v will cause the converter?s duty cycle to become unstable and ju mp to 100% duty cycle. for vin=3.0v, vout=2.5v, output load capability will be reduced since maximum duty cycle will occur at an output load level below 1a.
lx13088a p roduction d atasheet microsemi analog mixed signal group 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 12 copyright ? 2010 rev. 1.0, 2010-09-23 dual 1a step-down converters tm ? www. microsemi . com l l x x 1 1 3 3 0 0 8 8 8 8 a a package dimensions ld 10-pin plastic mlp dual exposed pad d e a a3 d2 e2 b l e a1 top view bottom view dim m illimeters i nches min max min max a 0.80 1.00 0.0315 0.0394 a1 0 0.05 0 0.0019 a3 0.20 ref 0.0079 ref b 0.18 0.30 0.0071 0.0118 d 3.00 bsc 0.1181 bsc d2 2.23 2.48 0.0878 0.0976 e 0.50 bsc 0.0197 bsc e 3.00 bsc 0.1181 bsc e2 1.49 1.74 0.0587 0.0685 l 0.30 0.50 0.0071 0.0197 note: 1. dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006?) on any side. lead dimension shall not include solder coverage. production data ? information contained in this document is proprietary to microsemi and is current as of publication date. this document may not be modified in any way without the express written consent of microsemi. product processing does not necessarily include testing of all parameters. microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time.

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